The present invention relates to a method and a device for designing a clock tree that distributes a clock signal in designing an LSI, and can be suitably used in designing a clock tree with low power consumption in particular.
CTS (Clock Tree Synthesis), which automatically generates a clock tree that distributes a clock signal from a clock supply point to leaves in designing an LSI (Large Scale Integrated circuit), tends to insert a large number of clock buffers in order to reduce a clock skew. This causes an increase in power consumption of the LSI.
CTS is a bottom-up clock tree design method of placing clock buffers to a clock supply point in a tree shape, with a large number of leaves at the ends of a clock tree as start points. More details are as follows, for example. Flip-flops and the like at the ends (leaves) of a clock tree are divided into groups, each of which is constituted by a plurality of leaves, and each group is driven with one clock buffer. A plurality of clock buffers each driving each group is divided into groups, and the respective groups are driven with one high level clock buffer. This is repeated until the number of highest level clock buffers becomes the number of clock buffers that can be driven by a clock supply point. The propagation delay of a clock signal from a clock supply point to a leaf is referred to as a latency, and a difference between the latencies is referred to as a clock skew. Although the clock skew is ideally zero, an allowable maximum value of the clock skew is given as a skew constraint. If the skew constraint cannot be satisfied, a clock buffer for increasing the latency is inserted into a path with a smaller latency of a clock tree to reduce the skew and thereby satisfy the skew constraint.
The method of forming a clock tree described in Japanese Patent Laid-Open No. 2009-152451 (Patent Document 1) is CTS that generates a clock tree from bottom up by grouping loads as uniformly as possible. For a clock buffer leading to a clock gate in a tree, the placement thereof is determined based on a distribution of clock gates (Paragraph 0034), and the number of stages is uniformly set (Paragraph 0018), and the number of stages of a clock buffer from a clock gate to a leaf is also uniformly set (Paragraph 0021), thereby suppressing the clock skew.
According to a gated clock synthesis method described in Japanese Patent Laid-Open No. 2001-306642 (Patent Document 2), fan-outs of a gated buffer are divided into the optimum number of groups based on a specified maximum number of fan-outs, and a gated logic and a gated buffer are inserted for each group, thereby suppressing the clock skew.
In CTS, as disclosed in Patent Document 1 and Patent Document 2, the fan-out of a clock buffer is attempted to be equalized, thereby suppressing the clock skew. However, because leaves are not always uniformly distributed within an LSI chip, a variation may occur in the routing length of a routing constituting a clock tree. The clock skew increases due to a variation in the routing length.
In contrast, there is a clock tree generation method, called H-tree, of generating a clock tree under a constraint that the driving from a clock buffer to the next stage clock buffer is performed with an equal load/equal-length routing. The H-tree is a top-down clock tree design method of sequentially placing buffers in a tree shape toward leaves with a clock supply point as a start point. An LSI chip is equally divided into two by a straight line passing through a clock supply point to form two regions, and the same clock buffer of the next stage is placed at the center of the respective regions. At the respective centers of the two regions, the distance from the clock supply point is set equal to each other and the size of the clock buffer is set to the same size, thereby placing the clock buffers having an equal load and an equal driving power, respectively. Because the routing load (resistance and capacitance) from the clock supply point to the first-stage buffer is equal and further the load of the buffer itself (input capacitance) is also equal, the signal propagation delay from the clock supply point to the first-stage buffer is theoretically equal to each other. That is, the clock skew becomes theoretically zero. Each region is further equally divided into two, and the same clock buffer of the next stage is placed at the respective centers. By repeating this, the constraint of the equal load/equal-length routing is maintained and the clock skew can be theoretically suppressed to zero. An LSI chip is sequentially equally-divided into two, four, eight equal regions, but in cases where leaves are not uniformly placed, a variation in fan-outs occurs in coupling to leaves and a clock skew is generated.
In Japanese Patent Laid-Open No. 2003-078014 (Patent Document 3), an upper stage with a clock supply point as a start point is constituted by H-tree, while a lower stage is formed by CTS. By restricting the placement position so that a clock driver generated by CTS is placed only within a certain region, coupling between an end of the H-tree and the start point of the CTS is simplified (Paragraph 0021, etc.).